1. Technical Field
The present invention relates generally to register file access control circuits, and more particularly to a register file having automatic read-after-write blocking.
2. Description of the Related Art
Register files are commonly used building blocks in digital circuits, particularly in processing system components where fast access to a fairly small quantity of data is required with low access latency. Examples of register file uses include register arrays in processors, cache directories in cache memories.
In contrast to static random access memory (SRAM) cells, register file cells are often written to and then read from within the same clock cycle. For processor core elements where register files are storing machine state information, register files are almost always read immediately after a write in the same clock cycle. Such register files are in the critical path that determines processor speed and as such, the write to read delays are finely tuned to provide the best performance possible within clock skew variation, voltage variation, and other factors that could cause the reading of false or unstable data.
Typical design margins for register file read-after-write timing may waste up to 30% of the clock cycle time by waiting until the write cycle is complete. But such margins are necessary within the typical ranges of the operational variables mentioned above and with current circuits used to implement register file cells and control logic.
Therefore, it would be desirable to further reduce the read-after-write margins to improve register file performance and the performance of processors using register files for storage of values and state information.